Full Adder Circuit. Part II

In this article we continue the investigations from [5] of verification of a design of adder circuit. We define it as a combination of 1-bit adders using schemes from [6]. n-bit adder circuit has the following structure 1st bit adder x 1 y 1 x 2 y 2 r 1 r 2 2nd bit adder nth bit adder x n y n r n As the main result we prove the stability of the circuit. Further works will consist of the proof of full cor-rectness of the circuit. [5] provide the notation and terminology for this paper. One can prove the following propositions: (1) For all sets x, y, z such that x = z and y = z holds {x, y} \ {z} = {x, y}. Let us observe that every many sorted signature which is void is also unsplit and has arity held in gates and Boolean denotation held in gates. One can verify that there exists a many sorted signature which is strict and void. Let x be a set. The functor SingleMSS x yielding a strict void many sorted signature is defined as follows: 1 The proposition (2) has been removed.